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LD7552B
1/2/2008
Green-Mode PWM Controller with Integrated Protections
Rev. 01a
General Description
The LD7552B are low cost, low startup current, current mode PWM controllers with green-mode power- saving operation. The integrated functions include the leading-edge blanking of the current sensing, internal slope compensation. They provide the users a superior AC/DC power application of higher efficiency, low external component counts, and lower cost solution. Furthermore, LD7552B feature more protections like OLP (Over Load Protection) and OVP (Over Voltage Protection) to eliminate the external protection circuits. It is designed for the switching adaptor with 30W~60W output, offered in both SOP-8 and DIP-8 package.
Features
High-Voltage CMOS Process with Excellent ESD protection Very Low Startup Current (<20A) Current Mode Control Non-audible-noise Green Mode Control UVLO (Under Voltage Lockout) LEB (Leading-Edge Blanking) on CS Pin Programmable Switching Frequency Internal Slope Compensation OVP (Over Voltage Protection) on Vcc Pin OLP (Over Load Protection) 500mA Driving Capability
Applications
Switching AC/DC Adaptor and Battery Charger Open Frame Switching Power Supply 384X Replacement
Typical Application
AC input EMI Filter
VCC
32V 16.0V /10.0V UVLO
OUT
RT COMP
LD7552B
OSC Control Logic
photocoupler
Divider
CS GND
TL431
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LD7552B
SOP-8 & DIP-8 (TOP VIEW) VCC OUT
Pin Configuration
8
7
6
NC
5
CS
TOP MARK YYWWPP
1 2 3 4
YY: Year code (D: 2004, E: 2005.....) WW: week code PP: production code
GND
VCC
Ordering Information
Part number LD7552B PS LD7552B GS LD7552B PN SOP-8 SOP-8 DIP-8 Package PB Free Green Package PB Free TOP MARK LD7552BPS LD7552BGS LD7552BPN Shipping 2500 /tape & reel 2500 /tape & reel 3600 /tube /carton
The LD7552B is ROHS Compliant/ Green Package.
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 NAME GND COMP photo-coupler to close the control loop and achieve the regulation. VCC RT to set the switching frequency. NC CS VCC OUT Unconnected pin Current sense pin, connect to sense the MOSFET current Supply voltage pin Gate drive output to drive the external MOSFET Supply voltage pin This pin is to program the switching frequency. By connecting a resistor to ground Ground Voltage feedback pin (same as the COMP pin in UC384X), By connecting a FUNCTION
COMP
RT
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LD7552B
Block Diagram
* Note: OLP delay is 60mS when the switching frequency is set as 65KHz.
The OLP delay time is proportional to the period of switching cycle. That is,
TOLP _ delay Ts =
1 . fs
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LD7552B
30V -0.3 ~7V 150C -40C to 85C -65C to 150C 160C/W 100C/W 400mW 650mW 260C 3KV 300V 500mA
Absolute Maximum Ratings
Supply Voltage VCC COMP, RT, CS Junction Temperature Operating Ambient Temperature Storage Temperature Range Package Thermal Resistance (SOP-8) Package Thermal Resistance (DIP-8) Power Dissipation (SOP-8, at Ambient Temperature = 85C) Power Dissipation (DIP-8, at Ambient Temperature = 85C) Lead temperature (Soldering, 10sec) ESD Voltage Protection, Human Body Model ESD Voltage Protection, Machine Model Gate Output Current
Caution:
Stresses beyond the ratings specified in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
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LD7552B
CONDITIONS MIN TYP 8 VCOMP=0V VCOMP=3V Protection tripped (OLP, OVP) 9.0 15.0 26.5 VCOMP=0V COMP pin open 2.0 2.5 0.5 10.0 16.0 28.0 1.5 6.0 2.35 0.80 1 100 RT=100K Fs=65KHz (-40C ~105C) (VCC=11V-25V) VCC=15V, Io=20mA VCC=15V, Io=20mA Load Capacitance=1000pF Load Capacitance=1000pF VCOMP(OLP) Fs=65KHz 9 50 30 5.0 60 160 60 60 65 20 5 1 1 70 0.85 350 0.90 11.0 17.0 29.5 2.2 MAX 20 3.0 UNITS A mA mA mA V V V mA V V V nS M nS KHz KHz % % V V nS nS V mS
Electrical Characteristics
(TA = +25 C unless otherwise stated, VCC=15.0V) PARAMETER Supply Voltage (Vcc Pin) Startup Current Operating Current (with 1nF load on OUT pin) UVLO (Off) UVLO (On) OVP Level Voltage Feedback (Comp Pin) Short Circuit Current Open Loop Voltage Green Mode Threshold VCOMP Current Sensing (CS Pin) Maximum Input Voltage, Vcs(off) Leading Edge Blanking Time Input impedance Delay to Output Oscillator (RT pin) Frequency Green Mode Frequency Temp. Stability Voltage Stability Gate Drive Output (OUT Pin) Output Low Level Output High Level Rising Time Falling Time OLP (Over Load Protection) OLP Trip Level OLP Delay Time (note)
o
Note: The OLP delay time is proportional to the period of switching cycle. frequency and the shorter OLP delay time.
So that, the lower RT value will set the higher switching
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LD7552B
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Typical Performance Characteristics
18.0
17.2
11.2
UVLO (on) (V)
UVLO (off) (V)
-40 0 40 80 120 125
16.4
10.4
15.6
9.6
14.8
8.8
14.0
8 -40 0 40 80 120 125
Temperature (C) Fig. 1 UVLO (on) vs. Temperature
Temperature (C) Fig. 2 UVLO (off ) vs. Temperature
70
26
Green Mode Frequency (KHz)
-40 0 40 80 120 125
68
24
Frequency (KHz)
66
22
64
20
62
18
60
16 -40 0 40 80 120 125
Temperature (C) Fig. 3 Frequency vs. Temperature
Temperature (C) Fig. 4 Green Mode Frequency vs. Temperature
70
25
68
Green Mode Frequency (KHz)
23
Frequency (KHz)
66
21
64
19
62
17
60 11
12
14
16
18
20
22
24
25
15 11
12
14
16
18
20
22
24
25
Vcc (V) Fig. 5 Frequency vs. Vcc
Vcc (V) Fig. 6 Green Mode Frequency vs. Vcc
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LD7552B
0.90 0.88
85
80
Max Duty (%)
75
VCS (off) (V)
-40 0 40 80 120 125
0.86
70
0.84
65
0.82
60
0.80
-40
0
40
80
120 125
Temperature (C) Fig. 7 Max Duty vs. Temperature
Temperature (C) Fig. 8 VCS (off) vs. Temperature
12
35
10 30 8
VCC OVP (V)
0 40 80 120 125
Istartup (A)
25
6
20
4
2
15
0 -40
10 -40
0
40
80
120 125
Temperature (C) Fig. 9 Startup Current (Istartup) vs. Temperature
Temperature (C) Fig. 10 VCC OVP vs. Temperature
7.0
6.0
6.5
5.5
VCOMP (V)
5.5
OLP (V)
0 40 80 120 125
6.0
5.0
4.5
5.0
4.0
4.5
-40
3.5 -40 0 40 80 120 125
Temperature (C) Fig. 11 VCOMP open loop voltage vs. Temperature
Fig. 12
Temperature (C) OLP-Trip Level vs. Temperature
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LD7552B
will help to increase the value of R1 and then reduce the power consumption on R1. By using CMOS process and the special circuit design, the maximum startup current of LD7552B is only 20A. If a higher resistance value of the R1 is chosen, it usually takes more time to start up. To carefully select the value of R1 and C1 will optimize the power consumption and startup time.
Application Information
Operation Overview
The LD7552B meet the green-power requirement and are intended for the use in those modern switching power suppliers and adaptors that demand higher power efficiency and power-saving. They integrated more functions to reduce the external component counts and the size. Their major features are described as below.
Under Voltage Lockout (UVLO)
An UVLO comparator is implemented in it to detect the voltage on the VCC pin. It would assure the supply voltage enough to turn on the LD7552B PWM controller and further to drive the power MOSFET. voltage dip during startup. As shown in Fig. 13, a The turn-on and turn-off hysteresis is built in to prevent the shutdown from the threshold level are set at 16.0V and 10.0V, respectively.
Vcc
UVLO(on) UVLO(off)
t I(Vcc)
operating current (~ mA)
Fig. 14
Current Sensing and Leading-edge Blanking
The typical current mode of PWM controller feedbacks both
startup current (~uA)
current signal and voltage signal to close the control loop
t
and achieve regulation. As shown in Fig. 15, the LD7552B detect the primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. The maximum voltage threshold of the current sensing pin is set at 0.85V. From above, the MOSFET peak current can be obtained from below.
IPEAK(MAX) = 0.85 V RS
Fig. 13
Startup Current and Startup Circuit
The typical startup circuit to generate the LD7552B Vcc is shown in Fig. 14. produced from During the startup transient, the Vcc is LD7552B to drive power MOSFET. lower than the UVLO threshold thus there is no gate pulse Therefore, the current through R1 will provide the startup current and to charge the capacitor C1. Whenever the Vcc voltage is high enough to turn on the LD7552B and further to deliver the gate drive signal, the supply current is provided from the auxiliary winding of the transformer. Lower startup current requirement on the PWM controller
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LD7552B
R1 D1
Vin
Cbulk
C1
VCC OUT
LD7552B
Comp GND CS
Rs
Fig. 15
A 350nS leading-edge blanking (LEB) time is included in the input of CS pin to prevent the false-trigger from the current spike. In the low power application, if the total pulse width of the turn-on spikes is less than 350nS and the negative spike on the CS pin doesn't exceed -0.3V, it could eliminated the R-C filter (as shown in the figure16). However, the total pulse width of the turn-on spike is decided by the output power, circuit design and PCB layout. It is strongly recommended to adopt a smaller R-C filter (as shown in figure 17) for higher power application to avoid the CS pin being damaged by the negative turn-on spike. Fig. 16
Output Stage and Maximum Duty-Cycle
An output stage of a CMOS buffer, with typical 500mA driving capability, is incorporated to drive a power MOSFET directly. And the maximum duty-cycle of LD7552B is limited to 75% to avoid the transformer saturation.
Oscillator and Switching Frequency
Connect a resistor from RT pin to GND according to the equation below to program the normal switching frequency:
fSW = 65.0 x 100(KHz ) RT(K )
Fig. 17
Voltage Feedback Loop
The operating frequency range for the LD7552B is recommended to set between 50KHz and 130KHz. The voltage feedback signal is provided from the TL431 at the secondary side through the photo-coupler to the COMP pin of the LD7552B. Similar to UC384X, the LD7552B would carry 2 diodes voltage offset at the stage to feed the voltage divider at the ratio of 1/3, that is,
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LD7552B
On the other hand, if the OVP condition is removed, the Vcc level will get back to normal level and the output will automatically return to the normal operation. The OVP levels are 28.0V 1.5V.
1 V-( PWM COMPARATOR ) = x (VCOMP - 2VF ) 3
A pull-high resistor is embedded internally and can be eliminated externally.
Internal Slope Compensation
In the conventional application, the problem of the stability is a critical issue for current mode controlling, when it operates in higher than 50% of the duty-cycle. As UC384X, It takes slope compensation from injecting the ramp signal of the RT/CT pin through a coupling capacitor. It therefore requires no extra design for the LD7552B since it has integrated it already.
On/Off Control
The LD7552B can be turned off by pulling COMP pin lower than 1.2V. The gate output pin of the LD7552B will be Fig. 18 disabled immediately under such condition. The off-mode can be released when the pull-low signal is removed.
Over Load Protection (OLP) Dual-Oscillator Green-Mode Operation
There are many different topologies has been implemented in different chips for the green-mode or power saving requirements such as "burst-mode control", "skipping-cycle mode", "variable off-time control "...etc. The basic operation theory of all these approaches intended to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduces the switching frequency. To protect the circuit from being damaged under over load condition or short condition, a smart OLP function is implemented in the LD7552B. The figure 19 shows the waveforms of the OLP operation. In this case, the feedback system will force the voltage loop proceed toward the saturation and then pull up the voltage on COMP pin (VCOMP). Whenever the VCOMP trips up to the OLP threshold 5V and stays longer than 60mS, the protection will activate and then turn off the gate output to stop the switching of power circuit. The 60mS delay time is to prevent the false trigger from the power-on and turn-off transient. By such protection mechanism, the average input power can be reduced to very low level so that the component temperature and stress can be controlled within the safe operating area.
OVP (Over Voltage Protection) on Vcc
The VGS ratings of the nowadays power MOSFETs are often limited up to max. 30V. To prevent the VGS from the fault condition, LD7552B are implemented an OVP function on Vcc. Whenever the Vcc voltage is higher than the OVP threshold voltage, the output gate drive circuit will be shutdown simultaneously thus to stop the switching of the power MOSFET until the next UVLO(on). The Vcc OVP function in LD7552B is an auto-recovery type protection. If the OVP condition, usually caused by the The Vcc feedback loop opened, is not released, the Vcc will tripped the OVP level again and re-shutdown the output. is working as a hiccup mode. operation. The figure 18 shows its
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LD7552B
VCC
UVLO(on) UVLO(off) OLP UVLO(off) OLP Reset
t
COMP
60mS
5.0V OLP trip Level
t OUT
Switching
Non-Switching
Switching
t
Fig. 19
Fault Protection
There are several critical protections were integrated in the LD7552B to prevent the power supply or adapter from being damaged. Those damages usually come from open or short condition on the pins of LD7552B. Under the conditions listed below, the gate output will turn off immediately to protect the power circuit --RT pin short to ground RT pin floating CS pin floating
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LD7552B
Reference Application Circuit #1 --- 40W (5V/2A & 12V/2.5A) Adapter with 2-Stage Startup Circuit
Pin < 0.3W when Pout = 0W
F1 FL1 FL2 R51B R51A C51 BD1 R2A C1 R2C R2E D3 C10 R3B D2 R6 R4B R5B D1 L2 R3A R4A C2 T1 L51 C53 CR51 R5A R121B R121A C121 L121 ZD121 12V C52 5V
AC input
R1A R1B NTC1
CX1
CY2 CY3
R99 GND
C4
C8
IC1 VCC OUT CS
C122 D4 CR121 Q1
C123
R100 GND
LD7552B
RT RT GND
R10
R14 C5
R9 R8 R54
photocoupler
COMP
C6
C55 CY1 R55 IC51
R52
R121
ZD122
R122
R53
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ZD51
IC2
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LD7552B
BOM
P/N R1A R1B R2A R2C R3A R3B R4A R4B R5A R5B R6 R8 R9 R10 R14 RT R51A R51B R121A R121B R52 R53 R54 R55 R99A R99B R100A R100B R121 R122 FL1 FL2 T1 L2 L51 L121 Component Value 1M, 1206 1M, 1206 510K, 1206 510K, 1206 1M, 1206 1M, 1206 100K, 1206 100K, 1206 100, 1206 100, 1206 10, 1206 0.47, 1W 1.5K, 0805 10, 1206 0, 0805 100K, 0805,1% 100, 1206 100, 1206 100, 1206 100, 1206 3.6K, 0805, 1% 2.49K, 0805, 1% 200, 0805 1K, 0805 N/A N/A N/A N/A 33K, 0805 1K, 0805 Leadtrend's Design Leadtrend's Design Leadtrend's Design Bead Core Leadtrend's Design Leadtrend's Design Open Open Original P/N C1 C2 C4 C5 C6 C8 C10 C51 C52 C53 C55 C121 C122 C123 CX1 CY1 CY2 CY3 D1 D2 D3 D4 ZD51 ZD121 ZD122 Q1 BD1 CR51 CR121 IC1 IC2 IC51 F1 Component Value 100F, 400V 1000pF, 1000V, 1206 10F, 50V 100pF, 50V, 0805 0.022F, 50V, 0805 33F, 50V 0.1F, 50V, 0805 1000pF, 250V, 1206 470F, 16V 1000F, 25V 0.01F, 50V, 0805 1000pF, 250V, 1206 1000F, 25V 470F, 16V 0.22F,X-cap 2200pF,Y-cap, class2 2200pF,Y-cap, class2 2200pF,Y-cap, class2 1N4007 PS102R 1N4148 1N4148 5V1B 7.5V, 1W 15V 6A, 600V 2A, 600V 10A, 100V 10A, 60V LD7552B EL817B TL431, 1% 250V,T2A Walter SSS6N60A 2KBP06M Y1010DN SBL1060CF Leadtrend EVERLIGHT L-tec (LZG) L-tec (LZG) L-tec (LZG) L-tec (LZG) X7R L-tec X7R L-tec (LZG) X7R X7R L-tec (LZG) X7R Note
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LD7552B
Package Information
SOP-8
Dimension in Millimeters Symbol Min
A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 0
Dimensions in Inches Min
5.004 3.988 1.753 0.508 1.346 0.229 0.254 6.198 1.270 0
Max
5.004 3.988 1.753 0.508 1.346 0.229 0.254 6.198 1.270 8
Max
0.197 0.157 0.069 0.020 0.053 0.009 0.010 0.244 0.050 8
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LD7552B
Package Information
DIP-8
Dimension in Millimeters Symbol Min A B C D E F I J L 9.017 6.096 ----0.356 1.143 2.337 2.921 7.366 0.381 Max 10.160 7.112 5.334 0.584 1.778 2.743 3.556 8.255 ---
Dimensions in Inches Min 0.355 0.240 --0.014 0.045 0.092 0.115 0.290 0.015 Max 0.400 0.280 0.210 0.023 0.070 0.108 0.140 0.325 ---
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order.
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LD7552B
Revision History
Rev. 00 01 01a Date 09/20/2006 01/29/2007 1/2/2008 Change Notice Original Specification. Revision: Block Diagram Revision: Green Package Option
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